MODULE: CSYM028 – Modern Computer Architecture 2023/24

Assessment Brief

Guidelines – Please read carefully:

• The University of Northampton’s Policy on Academic Integrity and Misconduct will be strictly implemented. For further information, click here.
• This is not a group project and by submitting this assignment you are asserting that this submission is entirely your own individual work. You may discuss the assignment with other students, but any work done should be your own. Sharing your work with another student or submitting work that was done by someone else may be deemed academic misconduct.

• Any use of AI tools (e.g., ChatGPT) in academic work must be undertaken in a manner which is ethical and transparent. Additional information on this can be found on the University position on Artificial Intelligence (AI). Use of AI tools within your work must be acknowledged, cited, and referenced. For further information, click here.

• You must submit all items of the assessment according to the submission procedure stated in this document. Failure to follow the submission procedure may result in a penalty or capped grade.

Deliverables:

All requirements (Task 1, 2 and 3 below) MUST be delivered to achieve a pass grade for this assignment. 

Task 1: IEEE Paper (80%)

Using VHDL,design and simulate a complex smart system for a specific application or solution using a n 8 bit microcontroller/microprocessor. The following objectives should be implemented for your complex smart system:

(i) Draw a schematic diagram of your complex smart system.

(ii) Write a VHDL code for your system.

(iii) Simulate your code to obtain a VHDL test bench code.

(iv) Generate a waveform output for your complex smart system.

Write a 4000-words project report of your design and simulation using the IEEE conference/journal format (You can download the IEEE paper template from this link

 https://www.ieee.org/conferences/publishing/templates.html). 

Your project report will be evaluated based on:

- Scientific merit

- Relevance

- Presentation

- Novelty

- Fundamental insights

- Evaluation

- Potential for long-term impact

This is an MSc assessment and as such should show good research and analytical skills. Note, 80% of your references (related work) should be from recent papers (2019-2023). It should be referenced using IEEE Citation Reference and should include information from refereed conferences and/or journals (papers from IEEE Xplore are highly recommended). As a guideline, if you include work which has been obtained from other sources e.g. books, journals, IEEE Xplore, ACM, internet – they must be referenced using the IEEE Citation scheme.

Task 2: Individual Laboratory Work (20%)

Complete and submit the design and simulation of the following class activities (10 devices), before your submission for Task 1 will be considered for grading.

1. 4-to-1 multiplexer
2. 2-to-4 decoder
3. 3-to-8 decoder
4. Letter Display System
5. D-flip flop
6. Full Adder
7. Digital Alarm Clock
8. Arithmetic Logic Unit (ALU)
9. 8-bit Comparator

10. 4-bit Up Counter

Your submission of each of the 10 devices in a word document will include:

(i) a schematic diagram of the device.

(ii) a VHDL code

(iii) a VHDL test bench code.

(iv) a waveform output

Task 3: Video Demonstration

In addition to the report, you must submit a video demo (URL) of your assignment. The demo should be about 10 minutes long and should cover all your work in a logical way.You should explain the main phases of design and implementation covering the main components of your work.Your face and voice need to be clear in the video. The module tutor reserves the right to invite you for an online viva-voce. Poor demo/viva could negatively influence other sections in the marking criteria and may result in a fail grade.You may also be referred for suspected academic misconduct.

Submission Procedure:

Submit Task 1 and 2 through Turnitin on NILE as TWO separate WORD documents. Task 3 will be submitted on NILE as a video link. To do this, go to the NILE site for this module and use the link labelled ‘Assessment and submission’.

• Task 1: The IEEE paper must be submitted electronically through Turnitin (via the link Task 1: IEEE Paper) and should be submitted as an editable “Microsoft Word” document.

Your submitted paper will be checked for any significant similarity to previously published (or submitted) works and should have a Turnitin similarity score below 25%. Also, take a snapshot of your VHDL code and VHDL test bench code of the complex system you designed and attach it to the end of the IEEE paper (after the references) as Appendix 1 and 2 respectively.

• Task 2: Submission will be electronically through Turnitin (Via the link Task 2: Individual Laboratory Work) and should be submitted as an editable “Microsoft Word” document.
• Task 3: When submitting your video demonstration, use of Kaltura (https://video.northampton.ac.uk/) is recommended. You must ensure that the video link is accessible to the marker (do not set it to private access).
  • Failure to follow the above submission guidelines may result in a capped or fail grade.